1. Technical Field
The present invention relates to integrated circuit processing, and more particularly to dense fin field effect transistor static random-access memory.
2. Description of the Related Art
FinFETs (fin field effect transistors) have become a viable device architecture for 22 nm nodes and beyond. However, the formation of finFET SRAM (static random-access memory) and finFET logic pose new challenges. One challenge is that some devices (e.g., logic FETs, multiple-finger pull down FETs/pass gate FETs) require epitaxy and a merged source/drain region while other devices (e.g., pull up FETs) only require epitaxy over the source/drain region, without the merging. Conventionally, dummy fins are utilized to accommodate the merge/unmerge issue. Unfortunately, dummy fins result a number of problems, such as an increase in SRAM cell size and tight overlay control in fin patterning (removing dummy fin).
For 10 nm nodes, there is no known solution for forming SRAM finFETs with fin pitch below 20 nm due to the lack of known patterning techniques to meet the tight overlay requirement.